7643 datasheet(76/424 Pages) RENESAS

76 / 424 page

Rev.2.00

Aug 28, 2006

page 59 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

RESET CIRCUIT

To reset the microcomputer, RESET pin should be held at an “L”

level for 20 cycles or more of

φ. Then the RESET pin is returned to

an “H” level, and reset is released. They must be performed when

the power source voltages are between 3.00 V and 3.60 V or 4.15

V and 5.25 V.

After the reset is completed, the program starts from the address

contained in address FFFA16 (high-order byte) and address

FFFB16 (low-order byte).

After oscillation has restarted, the timers 1 and 2 secures waiting

time for the internal clock

φ oscillation stabilized automatically by

setting the timer 1 to “FF16” and timer 2 to “0116”. The internal

clock

φ retains “H” level until Timer 2’s underflow and it cannot be

supplied until the underflow.

The pins state during reset are follows:

•When CNVss = “H”

Ports P0, P1, P33 to P37

: Outputting

Pins other than above mentioned ports

: Inputting

•When CNVss = “L”

All pins

: Inputting.

Fig. 54 Reset sequence

Fig. 53 Reset circuit example

(Note)

0.2VCC

Poweron

VCC

RESET

VCC

RESET

Power source

voltage detection

circuit

Power source

voltage

Reset input

voltage

Note : Reset release voltage ; Vcc = 3.00 or 4.15 V

RESET

Internal

reset

Data

Address

SYNC

XIN: 512 clock cycles

FFFA

FFFB

ADH,L

ADL

ADH

Reset address from

the vector table.

Notes: The question marks (?) indicate an undefined state that depends on the previous state.

7643 Datasheet(PDF) 76 Page - Renesas Technology Corp

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