7643 datasheet(10/424 Pages) RENESAS

10 / 424 page

Rev.2.00

Aug 28, 2006

page 6 of 12

7643 Group

REJ09B0133-0200

CHAPTER 2 APPLICATION

Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2

Fig. 2.1.2 Structure of Port Pi register .......................................................................................... 3

Fig. 2.1.3 Structure of Port P4, Port P7 registers ....................................................................... 3

Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) ................................. 4

Fig. 2.1.5 Structure of Port P4 direction, Port P7 direction registers ....................................... 4

Fig. 2.1.6 Structure of Port control register .................................................................................. 5

Fig. 2.1.7 Structure of Port P2 pull-up control register ............................................................... 5

Fig. 2.1.8 Structure of Interrupt request register C ..................................................................... 6

Fig. 2.1.9 Structure of Interrupt control register C ....................................................................... 6

Fig. 2.1.10 Registers setting ............................................................................................................ 7

Fig. 2.1.11 Connection diagram ...................................................................................................... 8

Fig. 2.1.12 Control procedure .......................................................................................................... 8

Fig. 2.2.1 Memory map of registers relevant to timers ............................................................. 12

Fig. 2.2.2 Structure of Timer i (i=1, 2, 3) .................................................................................... 13

Fig. 2.2.3 Structure of Timer 123 mode register ........................................................................ 13

Fig. 2.2.4 Structure of Interrupt request register B .................................................................... 14

Fig. 2.2.5 Structure of Interrupt request register C ................................................................... 14

Fig. 2.2.6 Structure of Interrupt control register B ..................................................................... 15

Fig. 2.2.7 Structure of Interrupt control register C ..................................................................... 15

Fig. 2.2.8 Timers connection and setting of division ratios ...................................................... 16

Fig. 2.2.9 Related registers setting .............................................................................................. 17

Fig. 2.2.10 Control procedure ........................................................................................................ 18

Fig. 2.2.11 Peripheral circuit example .......................................................................................... 19

Fig. 2.2.12 Timers connection and setting of division ratios .................................................... 19

Fig. 2.2.13 Relevant registers setting .......................................................................................... 20

Fig. 2.2.14 Control procedure ........................................................................................................ 21

Fig. 2.3.1 Memory map of registers related to serial I/O ......................................................... 23

Fig. 2.3.2 Structure of Serial I/O shift register ........................................................................... 24

Fig. 2.3.3 Structure of Serial I/O control register 1 ................................................................... 24

Fig. 2.3.4 Structure of Serial I/O control register 2 ................................................................... 25

Fig. 2.3.5 Structure of Interrupt request register C ................................................................... 26

Fig. 2.3.6 Structure of Interrupt control register C ..................................................................... 26

Fig. 2.3.7 Serial I/O connection examples (1) ............................................................................ 27

Fig. 2.3.8 Serial I/O connection examples (2) ............................................................................ 28

Fig. 2.3.9 Connection diagram ...................................................................................................... 29

Fig. 2.3.10 Timing chart ................................................................................................................. 29

Fig. 2.3.11 Registers setting for transmitter ................................................................................ 30

Fig. 2.3.12 Setting of serial I/O transmission data .................................................................... 30

Fig. 2.3.13 Control procedure of transmitter ............................................................................... 31

Fig. 2.3.14 Connection diagram .................................................................................................... 32

Fig. 2.3.15 Registers setting for SPI compatible mode ............................................................. 33

Fig. 2.3.16 Control procedure of SPI compatible mode in slave ............................................. 34

Fig. 2.3.17 Control procedure of SPI compatible mode in master .......................................... 35

List of figures

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