7643 datasheet(47/424 Pages) RENESAS

47 / 424 page

Rev.2.00

Aug 28, 2006

page 30 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

q SPI Compatible Mode Operation

Setting the SPI Mode Select Bit (bit 0 of SIOCON2) puts the serial

I/O in SPI compatible mode. The Synchronous Clock Select Bit

(bit 6 of SIOCON1) determines whether the serial I/O is an SPI

master or slave. When the external clock (SCLK pin input) is se-

lected (“0”), the serial I/O is in slave mode; When the internal

synchronous clock is selected (“1”), the serial I/O is in master

mode.

In SPI compatible mode the SRXD pin functions as a MISO (Mas-

ter In/Slave Out) pin and the STXD pin functions as a MOSI

(Master Out/Slave In) pin.

In slave mode the transmit data is output from the MISO pin and

the receive data is input from the MISO pin. The SRDY pin func-

tions as the chip-select signal input pin from an external.

In master mode the transmit data is output from the MOSI pin and

the receive data is input from the MISO pin. The SRDY pin func-

tions as the chip-select signal output pin to an external.

qSlave Mode Operation

In slave mode of SPI compatible mode 4 types of clock polarity

and clock phase can be usable by bits 3 and 4 of serial I/O control

If the SRDY pin is held “H”, the shift clock is inhibited, the serial I/

O counter is set to “7”. If the SRDY pin is held “L”, then the shift

clock will start.

Make sure during transfer to maintain the SRDY input at “L” and

not to write data to the serial I/O counter.

Figure 23 shows the serial I/O timing.

7643 Datasheet(PDF) 47 Page - Renesas Technology Corp