7643 datasheet(15/424 Pages) RENESAS

15 / 424 page

Rev.2.00

Aug 28, 2006

page 11 of 12

7643 Group

REJ09B0133-0200

Fig. 3.5.15 Structure of Port P2 pull-up control register ........................................................... 51

Fig. 3.5.16 Structure of USB control register ............................................................................. 51

Fig. 3.5.17 Structure of Clock control register ............................................................................ 52

Fig. 3.5.18 Structure of Timer i .................................................................................................... 53

Fig. 3.5.19 Structure of Timer 123 mode register ...................................................................... 53

Fig. 3.5.20 Structure of Serial I/O shift register ......................................................................... 54

Fig. 3.5.21 Structure of Serial I/O control register 1 ................................................................. 55

Fig. 3.5.22 Structure of Serial I/O control register 2 ................................................................. 55

Fig. 3.5.23 Structure of Timer UART mode register .................................................................. 56

Fig. 3.5.24 Structure of UART baud rate generator .................................................................. 56

Fig. 3.5.25 Structure of UART status regiseter .......................................................................... 57

Fig. 3.5.26 Structure of UART control register ........................................................................... 57

Fig. 3.5.27 Structure of UART transmit/receive buffer registers 1, 2 ...................................... 58

Fig. 3.5.28 Structure of UART RTS control register .................................................................. 59

Fig. 3.5.29 Structure of DMAC index and status register ......................................................... 60

Fig. 3.5.30 Structure of DMAC channel x mode register 1 (x = 0, 1) .................................... 61

Fig. 3.5.31 Structure of DMAC channel 0 mode register 2 ...................................................... 62

Fig. 3.5.32 Structure of DMAC channel 1 mode register 2 ...................................................... 63

Fig. 3.5.33 Structure of DMAC channel x source registers Low, High ................................... 64

Fig. 3.5.34 Structure of DMAC channel x destination registers Low, High ............................ 64

Fig. 3.5.35 Structure of DMAC channel x transfer count registers Low, High (x = 0, 1) .... 65

Fig. 3.5.36 Structure of USB address register ........................................................................... 66

Fig. 3.5.37 Structure of USB power management register ....................................................... 67

Fig. 3.5.38 Structure of USB interrupt status register 1 ........................................................... 68

Fig. 3.5.39 Structure of USB interrupt status register 2 ........................................................... 69

Fig. 3.5.40 Structure of USB interrupt enable register 1 .......................................................... 70

Fig. 3.5.41 Structure of USB interrupt enable register 2 .......................................................... 70

Fig. 3.5.42 Structure of USB endpoint index register ................................................................ 71

Fig. 3.5.43 Structure of USB endpoint x IN control register .................................................... 72

Fig. 3.5.44 Structure of USB endpoint x OUT control register (x = 1, 2) .............................. 73

Fig. 3.5.45 Structure of USB endpoint x IN max. packet size register (x = 0 to 2) ............ 74

Fig. 3.5.46 Structure of USB endpoint x OUT max. packet size register (x = 0 to 2) ........ 74

Fig. 3.5.47 Structure of USB endpoint x OUT write control register (x = 0 to 2) ................ 75

Fig. 3.5.48 Structure of USB endpoint FIFO mode register ..................................................... 75

Fig. 3.5.49 Structure of USB endpoint x FIFO register (x = 0 to 2) ....................................... 76

Fig. 3.5.50 Structure of Flash memory control register ............................................................. 77

Fig. 3.5.51 Structure of Frequency synthesizer control register .............................................. 78

Fig. 3.5.52 Structure of Frequency synthesizer multiply register 1 ......................................... 78

Fig. 3.5.53 Structure of Frequency synthesizer multiply register 2 ......................................... 79

Fig. 3.5.54 Structure of Frequency synthesizer divide register ................................................ 80

Fig. 3.5.55 Structure of ROM code protect control register ..................................................... 81

List of figures

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