7643 datasheet(84/424 Pages) RENESAS

84 / 424 page

Rev.2.00

Aug 28, 2006

page 67 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

Slow Memory Wait

The 7643 Group is equipped with the slow memory wait function

(Software wait, RDY wait, and Extended RDY wait: software wait

plus RDY input anytime wait) for easier interfacing with external

devices that have long access times. The slow memory wait func-

tion can be enabled in the memory expansion mode and

microprocessor mode. The appropriate wait mode is selected by

setting bits 0 to 3 of CPU mode register B (address 000116). This

function can extend the read cycle or write cycle only for access to

an external memory. However, this wait function cannot be en-

abled for access to addresses 000816 to 000F16.

(1) Software wait

The software wait is selected by setting “00” to the Slow Memory

Wait Mode Select Bits of CPU mode register B (address 000116).

Read/write cycles (“L” width of RD pin/WR pin) can be extended

by one to three

φ cycles. The number of cycles to be extended can

be selected with the Slow Memory Wait Select Bits. When the

software wait function is selected, the RDY pin status becomes in-

valid.

(2) RDY wait

RDY Wait is selected by setting “10” to the Slow Memory Wait

Mode Select Bits of CPU mode register B (address 000116). When

a fixed time of “L” is input to the RDY pin at the beginning of a

read/write cycle (before

φ cycle falls), the MCU goes to the RDY

state. The read/write cycle can then be extended by one to three

cycles. The number of

φ cycles to be added can be selected by

the Slow Memory Wait Bits.

(3) Software wait + Extended RDY wait

Extended RDY Wait is selected by setting “11” to the Slow

Memory Wait Mode Select Bits of CPU mode register B (address

000116). The read/write cycle can be extended when a fixed time

of “L” is input to the RDY pin at the beginning of a read/write cycle

(before

φ cycle falls). The RDY pin state is checked continually at

each fall of

φ cycle until the RDY pin goes to “H”. When “H” is in-

put to the RDY pin, the wait is released within 1, 2, or 3

φ cycles

(as selected with the Slow Memory Wait Bits).

Fig. 64 Software wait timing diagram

XIN

φ OUT

ADOUT

CPMB = 0016

CPMB = 0116

1-cycle software wait

No wait

CPMB = 0216

2-cycle software wait

CPMB = 0316

3-cycle software wait

Note: This diagram assumes

φ = XIN/2.

Fig. 65 RDY wait timing diagram

XIN

φ OUT

ADOUT

CPMB = 0816

CPMB = 0916

CPMB = 0A16

CPMB = 0B16

RDY

tsu

1-cycle RDY wait

No wait

2-cycle RDY wait

3-cycle RDY wait

tsu

Note: This diagram assumes

φ = XIN/2.

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