7643 datasheet(100/424 Pages) RENESAS

100 / 424 page

Rev.2.00

Aug 28, 2006

page 83 of 103

REJ09B0133-0200

OVERVIEW

FLASH MEMORY MODE

7643 Group

(3) Standard serial I/O Mode

The standard serial I/O mode inputs and outputs the software

commands, addresses and data needed to operate (read, pro-

gram, erase, etc.) the internal flash memory. This I/O is clock

synchronized serial. This mode requires the exclusive external

equipment (flash programmer).

The standard serial I/O mode is different from the parallel I/O

mode in that the CPU controls flash memory rewrite (uses the

CPU rewrite mode), rewrite data input and so forth. The standard

serial I/O mode is started by connecting “H” to the P36 (CE) pin

and “H” to the P81 (SCLK) pin and “H” to the CNVSS pin (apply 4.5

V to 5.25 V to Vpp from an external source), and releasing the re-

set operation. (In the ordinary microcomputer mode, set CNVss

pin to “L” level.)

This control program is written in the Boot ROM area when the

product is shipped from Renesas. Accordingly, make note of the

fact that the standard serial I/O mode cannot be used if the Boot

ROM area is rewritten in parallel I/O mode. Figures 79 and 80

show the pin connections for the standard serial I/O mode.

In standard serial I/O mode, serial data I/O uses the four serial I/O

pins SCLK, SRXD, STXD and SRDY (BUSY). The SCLK pin is the

transfer clock input pin through which an external transfer clock is

input. The STXD pin is for CMOS output. The SRDY (BUSY) pin

outputs “L” level when ready for reception and “H” level when re-

ception starts.

Serial data I/O is transferred serially in 8-bit units.

In standard serial I/O mode, only the User ROM area shown in

Figure 71 can be rewritten. The Boot ROM area cannot be rewrit-

ten.

In standard serial I/O mode, a 7-byte ID code is used. When there

is data in the flash memory, commands sent from the peripheral

unit (programmer) are not accepted unless the ID code matches.

Outline Performance (Standard Serial I/O

Mode)

In standard serial I/O mode, software commands, addresses and

data are input and output between the MCU and peripheral units

(flash programer, etc.) using 4-wire clock-synchronized serial I/O.

In reception, software commands, addresses and program data

are synchronized with the rise of the transfer clock that is input to

the SCLK pin, and are then input to the MCU via the SRXD pin. In

transmission, the read data and status are synchronized with the

fall of the transfer clock, and output from the STXD pin.

The STXD pin is for CMOS output. Transfer is in 8-bit units with

LSB first.

When busy, such as during transmission, reception, erasing or

program execution, the SRDY (BUSY) pin is “H” level. Accordingly,

always start the next transfer after the SRDY (BUSY) pin is “L”

level.

Also, data and status registers in a memory can be read after in-

putting software commands. Status, such as the operating state of

the flash memory or whether a program or erase operation ended

successfully or not, can be checked by reading the status register.

Here following explains software commands, status registers, etc.

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