7643 datasheet(12/424 Pages) RENESAS

12 / 424 page

Rev.2.00

Aug 28, 2006

page 8 of 12

7643 Group

REJ09B0133-0200

Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request ..... 89

Fig. 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request ....... 89

Fig. 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request .... 90

Fig. 2.5.16 Setting of relevant registers (1) ................................................................................ 92

Fig. 2.5.17 Setting of relevant registers (2) ................................................................................ 93

Fig. 2.5.18 Control procedure ........................................................................................................ 94

Fig. 2.6.1 1 frame image ............................................................................................................... 97

Fig. 2.6.2 Packet type .................................................................................................................... 97

Fig. 2.6.3 Transaction format ........................................................................................................ 98

Fig. 2.6.4 Communication sequence of control transfer ............................................................ 99

Fig. 2.6.5 Device state transition ................................................................................................ 102

Fig. 2.6.6 Memory map of registers related to USB ................................................................ 103

Fig. 2.6.7 Structure of USB control register .............................................................................. 104

Fig. 2.6.8 Structure of USB address register ............................................................................ 105

Fig. 2.6.9 Structure of USB power management register ....................................................... 106

Fig. 2.6.10 Structure of USB interrupt status register 1 ......................................................... 107

Fig. 2.6.11 Structure of USB interrupt status register 2 ......................................................... 108

Fig. 2.6.12 Structure of USB interrupt enable register 1, USB interrupt enable register 2 109

Fig. 2.6.13 Structure of USB endpoint index register .............................................................. 110

Fig. 2.6.14 Structure of USB endpoint x IN control register .................................................. 115

Fig. 2.6.15 Structure of USB endpoint x (x=1 to 2) OUT control register ........................... 117

Fig. 2.6.16 Structure of USB endpoint x (x=0 to 2) IN max. packet size register .............. 118

Fig. 2.6.17 Structure of USB endpoint x (x=0 to 2) OUT max. packet size register ......... 119

Fig. 2.6.18 Structure of USB endpoint x (x=0 to 2) OUT write count register .................... 120

Fig. 2.6.19 Structure of USB endpoint x (x=0 to 2) FIFO register ........................................ 121

Fig. 2.6.20 Structure of USB endpoint FIFO mode register ................................................... 121

Fig. 2.6.21 Structure of clock control register .......................................................................... 122

Fig. 2.6.22 Structure of frequency synthesizer control register .............................................. 123

Fig. 2.6.23 Frequency synthesizer connection and setting of division ratios ....................... 128

Fig. 2.6.24 Registers setting (1) ................................................................................................. 129

Fig. 2.6.25 Registers setting (2) ................................................................................................. 130

Fig. 2.6.26 Registers setting (3) ................................................................................................. 131

Fig. 2.6.27 Control procedure (1) (USB block initial setting) ................................................. 132

Fig. 2.6.28 Control procedure (2) (USB block generating) ..................................................... 133

Fig. 2.6.29 Control procedure (3) (endpoint initial setting) ..................................................... 134

Fig. 2.6.30 Registers setting (1) (USB endpoint 1 transmit) .................................................. 135

Fig. 2.6.31 Control procedure (USB endpoint 1 IN interrupt routine) ................................... 136

Fig. 2.6.32 Registers setting (USB endpoint 1 OUT receive) ................................................ 137

Fig. 2.6.33 Control procedure (USB endpoint 1 OUT interrupt routine) ............................... 138

Fig. 2.6.34 Structure of SET_ADDRESS request ..................................................................... 139

Fig. 2.6.35 Register setting (processing when SET_ADDRESS is received) ....................... 139

Fig. 2.6.36 Control procedure ...................................................................................................... 140

Fig. 2.6.37 Register setting (USB function interrupt routine) .................................................. 142

Fig. 2.6.38 Control procedure (USB function interrupt routine) .............................................. 143

Fig. 2.6.39 Register setting (USB suspend interrupt) .............................................................. 144

Fig. 2.6.40 Control procedure (USB suspend interrupt routine) ............................................. 145

Fig. 2.6.41 Register setting (USB resume interrupt) ................................................................ 146

Fig. 2.6.42 Control procedure (USB resume interrupt routine) .............................................. 147

Fig. 2.6.43 Connection diagram .................................................................................................. 148

Fig. 2.6.44 Register setting (1) ................................................................................................... 149

Fig. 2.6.45 Register setting (2) ................................................................................................... 150

Fig. 2.6.46 Register setting (3) ................................................................................................... 151

Fig. 2.6.47 Control procedure (1) ............................................................................................... 152

List of figures

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