7643 datasheet(9/424 Pages) RENESAS

9 / 424 page

Rev.2.00

Aug 28, 2006

page 5 of 12

7643 Group

REJ09B0133-0200

Fig. 46 Structure of USB endpoint x IN max. packet size register ....................................... 54

Fig. 47 Structure of USB endpoint x OUT max. packet size register ................................... 54

Fig. 48 Structure of USB endpoint x (x = 0 to 2) OUT write count registers ...................... 55

Fig. 49 Structure of USB endpoint x (x = 0 to 2) FIFO register ........................................... 55

Fig. 50 Structure of USB endpoint FIFO mode register .......................................................... 56

Fig. 51 Frequency synthesizer block diagram ........................................................................... 57

Fig. 52 Structure of frequency synthesizer control register .................................................... 58

Fig. 54 Reset sequence ............................................................................................................... 59

Fig. 53 Reset circuit example ...................................................................................................... 59

Fig. 55 Internal status at reset .................................................................................................... 60

Fig. 56 Ceramic resonator or quartz-crystal oscillator external circuit .................................. 61

Fig. 57 External clock input circuit ............................................................................................. 61

Fig. 58 Structure of clock control register ................................................................................. 62

Fig. 59 Clock generating circuit block diagram ......................................................................... 63

Fig. 60 State transitions of clock ................................................................................................ 64

Fig. 61 Memory maps in processor modes other than single-chip mode ............................. 65

Fig. 62 Structure of CPU mode register A ................................................................................ 66

Fig. 63 Structure of CPU mode register B ................................................................................ 66

Fig. 64 Software wait timing diagram ......................................................................................... 67

Fig. 65 RDY wait timing diagram ................................................................................................ 67

Fig. 66 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram 68

Fig. 67 Hold function timing diagram ......................................................................................... 69

Fig. 68 STA ($ zz), Y instruction sequence when EDMA enabled ........................................ 70

Fig. 69 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “0” .......... 70

Fig. 70 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “1” .......... 70

Fig. 71 Block diagram of built-in flash memory ........................................................................ 72

Fig. 72 Structure of flash memory control register ................................................................... 73

Fig. 73 CPU rewrite mode set/release flowchart ...................................................................... 74

Fig. 74 Program flowchart ............................................................................................................ 76

Fig. 75 Erase flowchart ................................................................................................................. 77

Fig. 76 Full status check flowchart and remedial procedure for errors ................................ 79

Fig. 77 Structure of ROM code protect control ......................................................................... 80

Fig. 78 ID code store addresses ................................................................................................. 81

Fig. 79 Pin connection diagram in standard serial I/O mode (1) ........................................... 85

Fig. 80 Pin connection diagram in standard serial I/O mode (2) ........................................... 86

Fig. 81 Timing for page read ....................................................................................................... 88

Fig. 82 Timing for reading status register ................................................................................. 88

Fig. 83 Timing for clear status register ...................................................................................... 89

Fig. 84 Timing for page program ................................................................................................ 89

Fig. 85 Timing for block erasing ................................................................................................. 90

Fig. 86 Timing for erase all blocks ............................................................................................. 90

Fig. 87 Timing for download ........................................................................................................ 91

Fig. 88 Timing for version information output ........................................................................... 92

Fig. 89 Timing for Boot ROM area output ................................................................................. 92

Fig. 90 Timing for ID check ......................................................................................................... 93

Fig. 91 ID code storage addresses ............................................................................................ 93

Fig. 92 Full status check flowchart and remedial procedure for errors ................................ 96

Fig. 93 Example circuit application for standard serial I/O mode .......................................... 97

Fig. 94 Passive components near LPF pin ............................................................................. 101

Fig. 95 Peripheral circuit ............................................................................................................ 101

Fig. 96 Timing chart after interrupt occurs .............................................................................. 103

Fig. 97 Time up to execution of interrupt processing routine ................................................ 103

List of figures

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