7643 datasheet(56/424 Pages) RENESAS

56 / 424 page

Rev.2.00

Aug 28, 2006

page 39 of 103

REJ09B0133-0200

OVERVIEW

FUNCTIONAL DESCRIPTION

7643 Group

(1) Cycle Steal Transfer Mode

When the DMAC Channel x (x = 0, 1) Transfer Mode Selection Bit

(DxTMS) is set to “0”, the respective DMAC Channel x operates in

the cycle steal transfer mode.

When a request of the specified transfer factor is generated, the

selected channel transfers one byte of data from the address indi-

cated by the Source Register into the address indicated by the

Destination Register.

There are two kinds of DMA transfer triggers supported: hardware

transfer factor and software trigger. Hardware transfer factors can

be selected by the DMACx (x = 0, 1) Hardware Transfer Request

source Bit (DxHR). To only use the Interrupt Request Bit, the inter-

rupt can be disabled by setting its Interrupt Enable Bit of Interrupt

Control Register to “0”.

The DMA transfer request as a software trigger can be generated

by setting the DMA Channel x (x = 0, 1) Software Transfer Trigger

Bit (DxSWT) to “1”.

The Source Registers and Transfer Destination Registers can be

either decreased or increased by 1 after transfer completion by

setting bits 0 to 3 in the DMAC Channel x (x = 0, 1) Mode Regis-

ter. When the Transfer Count Register underflows, the Source

Registers and Destination Registers are reloaded from their

latches if the DMAC Register Reload Disable Bit (DRLDD) is “0”.

The Transfer Count Register value is reloaded after an underflow

regardless of DRLDD setting. At the same time, the DMAC Inter-

rupt Request Bit and the DMA Channel x (x = 0, 1) Count Register

Underflow Flag are set to “1”.

The DMAC Channel x Disable After Count Register Underflow En-

able Bit (DxDAUE) is “1”, the DMAC Channel x Enable Bit

(DxCEN) goes to “0” at an under flows of Transfer Count Register.

By setting the DMAC Channel x (x = 0, 1) Register Reload Bit

(DxRLD) to “1”, the Source Registers, Destination Registers, and

Transfer Count Registers can be updated to the values in their re-

spective latches.

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