7643 datasheet(14/424 Pages) RENESAS

14 / 424 page

Rev.2.00

Aug 28, 2006

page 10 of 12

7643 Group

REJ09B0133-0200

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ...................................... 13

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ...................................... 13

Fig. 3.1.3 Timing diagram (1) ........................................................................................................ 14

Fig. 3.1.4 Timing diagram (2) ........................................................................................................ 15

Fig. 3.1.5 Timing diagram (3) ........................................................................................................ 15

Fig. 3.1.6 Timing diagram (4); Memory expansion and microprocessor modes .................... 16

Fig. 3.1.7 Timing diagram (5); Memory expansion and microprocessor modes .................... 17

Fig. 3.2.1 Power source current standard characteristics (Ta = 25 °C) ................................. 18

Fig. 3.2.2 CMOS output port P-channel side characteristics (Ta = 25 °C) ............................ 19

Fig. 3.2.3 CMOS output port P-channel side characteristics (Ta = 70 °C) ............................ 19

Fig. 3.2.4 CMOS output port N-channel side characteristics (Ta = 25 °C) ........................... 20

Fig. 3.2.5 CMOS output port N-channel side characteristics (Ta = 70 °C) ........................... 20

Fig. 3.2.6 Port P20–P27 at pull-up characteristics (Ta = 25 °C) .............................................. 21

Fig. 3.2.7 Port P20–P27 at pull-up characteristics (Ta = 70 °C) .............................................. 21

Fig. 3.3.1 Sequence of setting external interrupt active edge ................................................. 22

Fig. 3.3.2 Circuit example for the proper positions of the peripheral components ............... 28

Fig. 3.3.3 Passive components near LPF pin ............................................................................. 28

Fig. 3.3.4 Insulation connector connection .................................................................................. 28

Fig. 3.3.5 Initialization of processor status register ................................................................... 35

Fig. 3.3.6 Sequence of PLP instruction execution ..................................................................... 36

Fig. 3.3.7 Stack memory contents after PHP instruction execution ........................................ 36

Fig. 3.4.1 Wiring for the RESET pin ............................................................................................ 39

Fig. 3.4.2 Wiring for clock I/O pins .............................................................................................. 39

Fig. 3.4.3 Bypass capacitor across the Vss line and the Vcc line .......................................... 40

Fig. 3.4.4 Wiring for a large current signal line ......................................................................... 41

Fig. 3.4.5 Wiring for signal lines where potential levels change frequently ........................... 41

Fig. 3.4.6 Vss pattern on the underside of an oscillator .......................................................... 42

Fig. 3.4.7 Setup for I/O ports ........................................................................................................ 42

Fig. 3.4.8 Watchdog timer by software ........................................................................................ 43

Fig. 3.5.1 Structure of CPU mode register A ............................................................................. 44

Fig. 3.5.2 Structure of CPU mode register B ............................................................................. 44

Fig. 3.5.3 Structure of Interrupt request register A .................................................................... 45

Fig. 3.5.4 Structure of Interrupt request register B .................................................................... 45

Fig. 3.5.5 Structure of Interrupt request register C ................................................................... 46

Fig. 3.5.6 Structure of Interrupt control register A ..................................................................... 46

Fig. 3.5.7 Structure of Interrupt control register B ..................................................................... 47

Fig. 3.5.8 Structure of Interrupt control register C ..................................................................... 47

Fig. 3.5.9 Structure of Port Pi ....................................................................................................... 48

Fig. 3.5.10 Structure of Port P4, Port P7 .................................................................................... 48

Fig. 3.5.11 Structure of Port Pi direction register ...................................................................... 49

Fig. 3.5.12 Structure of Port P4, Port P7 direction registers ................................................... 49

Fig. 3.5.13 Structure of Port control register .............................................................................. 50

Fig. 3.5.14 Structure of Interrupt polarity select register .......................................................... 50

List of figures

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