7643 datasheet(139/424 Pages) RENESAS

139 / 424 page

Rev.2.00

Aug 28, 2006

page 18 of 202

7643 Group

REJ09B0133-0200

APPLICATION

2.2 Timer

Fig. 2.2.10 Control procedure

RESET

SEI

CPMA

T123M

CLI

10111XXX2

00XX011X2

IREQB

6316

(address 2516)

(address 0316), bit7

(address 0016)

(address 2916)

(address 0316)

(address 0616)

(address 2916), bit1

Clock is stopped ?

IREQB (address 0316), bit7 ?

Initialization

•All interrupts disabled

•Timer count start

•Interrupts enabled

q X: This bit is not used here. Set it to “0” or “1” arbitrarily.

•Connection of Timers 1 and 2

•Setting of Interrupt request bits of Timers 1 and 2 to “0”

•Timer 1 interrupt enabled, Timer 2 interrupt disabled

•Setting “Division ratio – 1” to Timers 1 and 2

IREQB (address 0316), bit7

✽

Clock count up

Second to Year

Main processing

•Judgment whether time is not set or time is being set

•Confirmation that 1 s has passed

(Check of Timer 2 interrupt request bit)

•Interrupt request bit cleared

(Clear it by software when not using the interrupt.)

•Clock count up

•Adjust the main processing so that all processing in the loop ✽ will

be processed within 1 s interval.

•Set Timers again when starting clock from 0 s after end of

clcok setting.

•Do not set Timer 1 again because Timer 1 is used to

generate the interrupt at 10 ms intervals.

Note : Perform procedure for end of clock setting only when end of

clock setting.

<Procedure for end of clock setting> (Note)

IREQB

ICONB

(address 2416)

(address 2516)

9F16

6316

00XXXXXX2

0100000X2

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