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7643 Datasheet(PDF) 146 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 146 Page - Renesas Technology Corp |
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146 / 424 page  Rev.2.00 Aug 28, 2006 page 25 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.3 Serial I/O Fig. 2.3.4 Structure of Serial I/O control register 2 Serial I/O control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register 2 (SIOCON2 : address 2C16) b 0 00 0 0 1 2 4 Name 0 Functions At reset R W 0 0 1 1 Clock polarity select bit (CPoL) Clock phase select bit (CPha) SRXD input enable bit 0 : Normal serial I/O mode 1 : SPI compatible mode (Note) 0 : SRXD input disabed 1 : SRXD input enabed 0 : SCLK starting at “L” 1 : SCLK starting at “H” 0 : Serial transfer starting at falling edge of SRDY 1 : Serial transfer starting after a half cycle of SCLK passed at falling edge of SRDY 7 0 0 0 SPI mode select bit Nothing is arranged for these bits. Fix these bits to “0”. 3 5 6 Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”. Nothing is arranged for this bit. Fix this bit to “0”. |
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