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7643 Datasheet(PDF) 281 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 281 Page - Renesas Technology Corp |
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281 / 424 page  Rev.2.00 Aug 28, 2006 page 160 of 202 7643 Group REJ09B0133-0200 APPLICATION 2.6 USB Fig. 2.6.55 Control procedure (2) UART receive buffer full interrupt RTI Pop registers Y Push registers to stack • The contents of USB receive buffer is written to USB endpoint 1 FIFO. P40=“H”? USBINDEX (Address 5816) IN_CSR (Address 5916) UCON (Address 3316), bit1 Interrupt occurs N • Receive operation completed USB transmit processing When one-packet data is received, USB transmit is enabled. Receive is disabled. X00000012 0XXXXXX12 0 USBFIFO1 UTRB1(Address 3416) (Address 6116) UART summing error interrupt RTI P41 NOP P41 • “L” pulse is generated on P41, and re-transmit is requested to host CPU. 0 1 A register A register • Read UART status register and clear error flag. • Read out USB receive buffer to make it be empty. USTS (Address 3216) UTRB1 (Address 3416) Pop registers Push registers to stack Interrupt occurs |
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