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UJA1075TW/5V0/WD Datasheet(PDF) 14 Page - NXP Semiconductors

Part # UJA1075TW/5V0/WD
Description  High-speed CAN/LIN core system basis chip
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

UJA1075TW/5V0/WD Datasheet(HTML) 14 Page - NXP Semiconductors

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UJA1075_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 May 2010
14 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
6.2.5 Int_Control register
Table 6.
Int_Control register
Bit
Symbol
Access
Power-on
default
Description
15:13
A2, A1, A0 R
010
register address
12
RO
R/W
0
access status
0: register set to read/write
1: register set to read only
11
V1UIE
R/W
0
V1 undervoltage interrupt enable
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
10
V2UIE
R/W
0
V2 undervoltage interrupt enable
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
9
STBCL
R/W
0
LIN standby control
0: When the SBC is in Normal mode (MC = 1x):
LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared
regardless of the value of VBAT.
When the SBC is in Standby/Sleep mode (MC = 0x):
LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up
interrupts cannot be requested.
1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless
of the SBC mode (MC = xx). LIN wake-up interrupts can be requested.
8
reserved
R
0
7:6
WIC1
R/W
00
wake-up interrupt 1 control
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
5:4
WIC2
R/W
00
wake-up interrupt 2 control
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
3
STBCC
R/W
0
CAN standby control
0: When the SBC is in Normal mode (MC = 1x):
CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared
regardless of V2 output voltage.
When the SBC is in Standby/Sleep mode (MC = 0x):
CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up
interrupts cannot be requested.
1: CAN is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be
requested.



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