UJA1075TWSLASH5V0SLASHWD datasheet(26/53 Pages) NXP

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

26 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

edge on pin TXDL. If the pin remains LOW for longer than the TXDL dominant time-out

time (tto(dom)TXDL), the transmitter is disabled, driving the bus lines to a recessive state.

The timer is reset by a positive edge on the TXDL pin.

6.9 Local wake-up input

The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity

(falling, rising or both) of the wake-up pins can be configured independently via the WIC1

and WIC2 bits in the Int_Control register Table 6). These bits can also be used to disable

wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either

of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal

mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and

enter Standby mode. The status of the wake-up pins can be read via the wake-up level

status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4).

Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts

is enabled (WIC1

≠ 00 or WIC2 ≠ 00).

The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting

bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are

sampled continuously). The sampling will be performed on the rising edge of WBIAS (see

Figure 11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit

(WBC) in the Mode_Control register.

Figure 12 shows typical circuit for implementing cyclic sampling of the wake-up inputs.

Fig 11. Wake-up pin sampling synchronized with WBIAS signal

Wake-up int

WAKEx pin

WBIAS pin

WBIASI

(internal)

enable bias

disable bias

wake level latched

015aaa078

UJA1075TW/5V0/WD Datasheet(PDF) 26 Page - NXP Semiconductors