UJA1075TWSLASH5V0SLASHWD datasheet(16/53 Pages) NXP

16 / 53 page

UJA1075_2

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 02 — 27 May 2010

16 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

6.2.6 Int_Status register

[1]

An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.

6.3 On-chip oscillator

The on-chip oscillator provides the timing reference for the on-chip watchdog and the

internal timers. The on-chip oscillator is supplied by an internal supply that is connected to

VBAT and is independent of V1/V2.

Table 7.

Int_Status register[1]

Bit

Symbol

Access

Power-on

default

Description

15:13

A2, A1, A0 R

011

R/W

access status

0: register set to read/write

1: register set to read only

V1UI

R/W

V1 undervoltage interrupts

0: no V1 undervoltage warning interrupt pending

1: V1 undervoltage warning interrupt pending

V2UI

R/W

V2 undervoltage interrupts

0: no V2 undervoltage warning interrupt pending

1: V2 undervoltage warning interrupt pending

LWI

R/W

LIN wake-up interrupt

0: no LIN wake-up interrupt pending

1: LIN wake-up interrupt pending

reserved

R/W

cyclic interrupt

0: no cyclic interrupt pending

1: cyclic interrupt pending

WI1

R/W

wake-up interrupt 1

0: no wake-up interrupt 1 pending

1: wake-up interrupt 1 pending

POSI

R/W

power-on status interrupt

0: no power-on interrupt pending

1: power-on interrupt pending

WI2

R/W

wake-up interrupt 2

0: no wake-up interrupt 2 pending

1: wake-up interrupt 2 pending

CWI

R/W

CAN wake-up interrupt

0: no CAN wake-up interrupt pending

1: CAN wake-up interrupt pending

2:0

reserved

000

UJA1075TW/5V0/WD Datasheet(PDF) 16 Page - NXP Semiconductors

UJA1075TW/5V0/WD Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL