UJA1075TWSLASH5V0SLASHWD datasheet(28/53 Pages) NXP

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

28 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

Limiting values

Table 8.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

voltage on pin x

DC value

pins V1, V2 and INTN

−0.3

pins TXDC, RXDC, EN, SDI, SDO, SCK, SCSN,

TXDL, RXDL, RSTN and WDOFF

−0.3

VV1 + 0.3

pin VEXCC

VV1 − 0.3

VV1 + 0.35 V

pins WAKE1, WAKE2 and WBIAS; with respect to

any other pin

−58

+58

pin LIMP and BAT

−0.3

+40

pin VEXCTRL

−0.3

VBAT + 0.3 V

pins CANH, CANL, SPLIT and LIN; with respect to

any other pin

−58

+58

pin DLIN; with respect to any other pin

VBAT − 0.3 +58

IR(V1-BAT)

reverse current from

pin V1 to pin BAT

VV1 ≤ 5V

[1]

250

IDLIN

current on pin DLIN

−65

Vtrt

transient voltage

on pins

BAT: via reverse polarity diode/capacitor

CANL, CANH, SPLIT: coupling with two capacitors

on the bus lines

LIN: coupling via 1 nF capacitor

DLIN: via 1 k

Ω resistor

[2]

−150

+100

VESD

electrostatic

discharge voltage

IEC 61000-4-2

[3]

pins BAT with capacitor, CANH, CANL and LIN; via

a series resistor on pins SPLIT, DLIN, WAKE1 and

WAKE2

[4]

−6+6

HBM

[5]

pins CANH, CANL, LIN, SPLIT, DLIN, WAKE1 and

WAKE2

[6]

−8+8

pin BAT; referenced to ground

−4+4

pin TEST2; referenced to pin BAT

−1.25

pin TEST2; referenced to other reference pins

−2+2

any other pin

−2+2

[7]

any pin

−300

+300

CDM

[8]

corner pins

−750

+750

any other pin

−500

+500

Tvj

virtual junction

temperature

[9]

−40

+150

°C

Tstg

storage temperature

−55

+150

°C

UJA1075TW/5V0/WD Datasheet(PDF) 28 Page - NXP Semiconductors

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