UJA1075TWSLASH5V0SLASHWD datasheet(46/53 Pages) NXP

46 / 53 page

UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

46 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

12. Package outline

Fig 20. Package outline SOT549-1 (HTSSOP32)

UNIT

cD(1)

E(2)

eHE

LLp

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

0.15

0.05

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT549-1

03-04-07

05-11-02

w M

L p

detail X

exposed die pad side

(A3)

0.25

0.95

0.85

0.30

0.19

5.1

4.9

3.6

3.4

0.20

0.09

11.1

10.9

6.2

6.0

8.3

7.9

0.65

0.2

0.78

0.48

0.1

0.75

0.50

v M A

HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;

body width 6.1 mm; lead pitch 0.65 mm; exposed die pad

SOT549-1

max.

1.1

2.5

5 mm

scale

pin 1 index

MO-153

UJA1075TW/5V0/WD Datasheet(PDF) 46 Page - NXP Semiconductors

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