UJA1075TWSLASH5V0SLASHWD datasheet(29/53 Pages) NXP

29 / 53 page

UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

29 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

[1]

A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-).

[2]

Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.

[3]

IEC 61000-4-2 (150 pF, 330

Ω).

[4]

ESD performance according to IEC 61000-4-2 (150 pF, 330

Ω) has been verified by an external test house for pins BAT, CANH, CANL,

LIN1, LIN2, WAKE1 and WAKE2. The result is equal to or better than

±6 kV.

[5]

Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k

Ω).

[6]

V1, V2 and BAT connected to GND, emulating application circuit.

[7]

Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75

μH, 10 Ω).

[8]

Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).

[9]

In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =Tamb +P × Rth(vj-a), where Rth(vj-a) is a

fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient

temperature (Tamb).

Tamb

ambient

temperature

−40

+125

°C

Table 8.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

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