UJA1075TWSLASH5V0SLASHWD datasheet(18/53 Pages) NXP

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

18 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

• the SBC is in Standby mode and bit WMC = 0 or

• the SBC is in Normal mode and bit WMC = 1

6.4.3 Watchdog Off behavior

The watchdog is disabled in this state.

The watchdog is in Off mode when:

• the SBC is in Off, Overtemp or Sleep modes

• the SBC is in Standby mode and bit WMC = 1

• the SBC is in any mode and the WDOFF pin is HIGH

6.5 System reset

The following events will cause the SBC to perform a system reset:

• V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN

pin)

• An external reset (RSTN forced LOW)

• Watchdog overflow (Window mode)

• Watchdog overflow in Timeout mode with cyclic interrupt (CI) pending

• Watchdog triggered too early in Window mode

• WMC value changed in Normal mode

• WDOFF pin state changed

• SBC goes to Sleep mode (MC set to 01; see Table 5) while INTN is driven LOW

• SBC goes to Sleep mode (MC set to 01; see Table 5) while

STBCC = STBCL = WIC1 = WIC2 = 0

• SBC goes to Sleep mode (MC set to 01; see Table 5) while wake-up pending

• Software reset (SWR = 1)

• SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor

on RSTN pin)

A watchdog overflow in Timeout mode requests a cyclic interrupt (CI), if a CI is not already

pending.

The UJA1075 provides three signals for dealing with reset events:

• RSTN input/output for performing a global ECU system reset or forcing an external

reset

• EN pin, a fail-safe global enable output

• LIMP pin, a fail-safe limp home output

6.5.1 RSTN pin

A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least tfltr by

the microcontroller (external reset). A reset pulse is output on RSTN by the SBC when a

system reset is triggered internally.

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