UJA1075TWSLASH5V0SLASHWD datasheet(43/53 Pages) NXP

43 / 53 page

UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

43 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

[7]

The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the

watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than

ttrig(wd)2 after the start of the watchdog period (watchdog overflows).

Fig 15. Timing test circuit for CAN transceiver

Fig 16. CAN transceiver timing diagram

SBC

BAT

CANL

CANH

TXDC

RCANH − RCANL

RXDC

CRXDC

GND

CCANH − CCANL

015aaa079

CANH

CANL

td(TXDC-busdom)

TXDC

VO(dif)bus

RXDC

HIGH

LOW

dominant

recessive

0.9 V

0.5 V

td(busdom-RXDC)

td(TXDC-busrec)

td(busrec-RXDC)

td(TXDCH-RXDCH)

td(TXDCL-RXDCL)

015aaa151

UJA1075TW/5V0/WD Datasheet(PDF) 43 Page - NXP Semiconductors

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