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UJA1075TW/5V0/WD Datasheet(PDF) 40 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 53 page  UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 40 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip 10. Dynamic characteristics Table 11. Dynamic characteristics Tvj = −40 °C to +150 °C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; RLIN =500 Ω; R(CANH- CANL) = 45 Ω to 65 Ω; all voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Voltage source; pin V1 td(uvd) undervoltage detection delay time VV1 falling; dVV1/dt = 0.1 V/μs7 - 23 μs tdet(CL)L LOW-level clamping detection time VV1 <0.9VO(V1)nom; V1 active 95 - 140 ms Voltage source; pin V2 td(uvd) undervoltage detection delay time VV2 falling, dVV2/dt = 0.1 V/us 7 - 23 μs Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO tcy(clk) clock cycle time VV1 = 2.97 V to 5.5 V 320 - - ns tSPILEAD SPI enable lead time VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select falls 110 - - ns tSPILAG SPI enable lag time VV1 = 2.97 V to 5.5 V; clock is LOW when SPI select rises 140 - - ns tclk(H) clock HIGH time VV1 = 2.97 V to 5.5 V 160 - - ns tclk(L) clock LOW time VV1 = 2.97 V to 5.5 V 160 - - ns tsu(D) data input set-up time VV1 = 2.97 V to 5.5 V 0 - - ns th(D) data input hold time VV1 = 2.97 V to 5.5 V 80 - - ns tv(Q) data output valid time pin SDO; VV1 = 2.97 V to 5.5 V CL = 100 pF -- 110 ns tWH(S) chip select pulse width HIGH VV1 = 2.97 V to 5.5 V 20 - - ns Reset output; pin RSTN tw(rst) reset pulse width long; Ipu(RSTN) < 100 μA; no pull-up 20 - 25 ms short; Rpu(RSTN) = 900 Ω to 1100 Ω 3.6 - 5 ms tdet(CL)L LOW-level clamping detection time RSTN driven HIGH internally but RSTN remains LOW 95 - 140 ms tfltr filter time 7 - 18 μs Watchdog off input; pin WDOFF tfltr filter time 0.9 - 2.3 ms Wake input; pin WAKE1, WAKE2 twake wake-up time 10 - 40 μs td(po) power-on delay time 113 - 278 μs CAN transceiver timing; pins CANH, CANL, TXDC and RXDC td(TXDCH-RXDCH) delay time from TXDC HIGH to RXDC HIGH 50 % VTXDC to 50 % VRXDC VV2 = 4.5 V to 5.5 V R(CANH-CANL) = 60 Ω C(CANH-CANL) = 100 pF; CRXDC = 15 pF fTXDC = 250 kHz 60 - 235 ns |
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