UJA1075TWSLASH5V0SLASHWD datasheet(17/53 Pages) NXP

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UJA1075_2

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Product data sheet

Rev. 02 — 27 May 2010

17 of 53

NXP Semiconductors

UJA1075

High-speed CAN/LIN core system basis chip

6.4 Watchdog (UJA1075/xx/WD versions)

Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is

programmed via the NWP control bits in the WD_and_Status register (see Table 4). The

default watchdog period is 128 ms.

A watchdog trigger event is any write access to the WD_and_Status register. When the

watchdog is triggered, the watchdog timer is reset.

In watchdog Window mode, a watchdog trigger event within a closed watchdog window

(i.e. the first half of the window before ttrig(wd)1) will generate an SBC reset. If the watchdog

is triggered before the watchdog timer overflows in Timeout or Window mode, or within

the open watchdog window (after ttrig(wd)1 but before ttrig(wd)2), the timer restarts

immediately.

The following watchdog events result in an immediate system reset:

• the watchdog overflows in Window mode

• the watchdog is triggered in the first half of the watchdog period in Window mode

• the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending

• the state of the WDOFF pin changes in Normal mode or Standby mode

• the watchdog mode control bit (WMC) changes state in Normal mode

After a watchdog reset (short reset; see Section 6.5.1 and Table 11), the default watchdog

period is selected (NWP = 100). The watchdog can be switched off completely by forcing

pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in

Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will

re-enable it.

Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is

pending. Any attempt to change WMC when an interrupt is pending will be ignored.

6.4.1 Watchdog Window behavior

The watchdog runs continuously in Window mode.

If the watchdog overflows, or is triggered in the first half of the watchdog period (less than

ttrig(wd)1 after the start of the watchdog period), a system reset will be performed.

Watchdog overflow occurs if the watchdog is not triggered within ttrig(wd)2 after the start of

watchdog period.

If the watchdog is triggered in the second half of the watchdog period (at least ttrig(wd)1, but

not more than ttrig(wd)2, after the start of the watchdog period), the watchdog will be reset.

The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode

and the watchdog mode control bit (WMC) is set to 0.

6.4.2 Watchdog Timeout behavior

The watchdog runs continuously in Timeout mode. It can be reset at any time by a

watchdog trigger. If the watchdog overflows, the cyclic interrupt (CI) bit is set. If a CI is

already pending, a system reset is performed.

The watchdog is in Timeout mode when pin WDOFF is LOW and:

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