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UJA1075TW/5V0/WD Datasheet(PDF) 50 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD Datasheet(HTML) 50 Page - NXP Semiconductors |
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50 / 53 page ![]() UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 50 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes UJA1075_2 20100527 Product data sheet - UJA1075_1 Modifications: • Template upgraded to Rev. 2.11 including revised legal information • Figure 16, Figure 18: revised • Table 4: bit 7: WOS revised • Table 8: revised values/conditions - VESD, IR(V1-BAT) • Table 9: added • Table 10: revised parameter values/conditions - Vth(cntr)RX, Vth(hys)RX, VOL for RSTN pin, IO for LIMP pin; R(BAT-V1); Vuvr for pin V1 • Table 11: revised parameter values/conditions - tdet(CL)L for RSTN pin • Section 6.7.1.2, Section 6.8.1.2, Table 11: parameters renamed to twake(busdom)min, twake(busrec)min UJA1075_1 20091125 Product data sheet - - |
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