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UJA1075TW/5V0/WD Datasheet(PDF) 7 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 53 page  UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 7 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip 6.1 System Controller 6.1.1 Introduction The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in Figure 3. These modes are discussed in more detail in the following sections. |
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