TMS320C6743CPTP2 datasheet(3/151 Pages) TI1

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TMS320C6743

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SPRS565D – APRIL 2009 – REVISED JUNE 2014

1.3

Description

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device

consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers

(ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a

32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache.

The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program

and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output

(MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers

and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up

to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event

generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS);

three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced

capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width

modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2

external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower

memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the

network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half-

or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE

TMS320C6743

BGA (256)

17.00 mm x 17.00 mm

TMS320C6743

HLQFP (176)

24.00 mm x 24.00 mm

(1)

For more information on these devices, see Section 8, Mechanical Packaging and Orderable

Information.

TMS320C6743 Fixed- and Floating-Point Digital Signal Processor

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