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TMS320C6743CPTP2 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6743CPTP2 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 151 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320C6743 www.ti.com SPRS565D – APRIL 2009 – REVISED JUNE 2014 TMS320C6743 Fixed- and Floating-Point Digital Signal Processor 1 TMS320C6743 Fixed- and Floating-Point Digital Signal Processor 1.1 Features 1 – Normalization, Saturation, Bit-Counting • Applications – Compact 16-Bit Instructions – Networking • C674x Two-Level Cache Memory Architecture – High-Speed Encoding – 32KB of L1P Program RAM/Cache – Professional Audio™ – 32KB of L1D Data RAM/Cache • Software Support – 128KB of L2 Unified Mapped RAM/Cache – TI DSP/BIOS™ – Flexible RAM/Cache Partition (L1 and L2) – Chip Support Library and DSP Library • Enhanced Direct Memory Access Controller 3 • 375-MHz TMS320C674x Fixed- and Floating-Point (EDMA3): VLIW DSP Core – 2 Transfer Controllers – Load-Store Architecture with Nonaligned Support – 32 Independent DMA Channels – 64 General-Purpose Registers (32-Bit) – 8 Quick DMA Channels – Six ALU (32- and 40-Bit) Functional Units – Programmable Transfer Burst Size • 3.3-V LVCMOS I/Os • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double • Two External Memory Interfaces: Precision/64-Bit) Floating Point – EMIFA • Supports up to Four SP Additions Per Clock, • NOR (8-Bit-Wide Data) Four DP Additions Every 2 Clocks • NAND (8-Bit-Wide Data) • Supports up to Two Floating Point (SP or – EMIFB DP) Reciprocal Approximation (RCPxP) and • 16-bit SDRAM, up to 128MB Square-Root Reciprocal Approximation • Two Configurable 16550-Type UART Modules: (RSQRxP) Operations Per Cycle – UART0 with Modem Control Signals – Two Multiply Functional Units – 16-Byte FIFO • Mixed-Precision IEEE Floating Point Multiply – 16x or 13x Oversampling Option Supported up to: • One Serial Peripheral Interface (SPI) with One – 2 SP x SP -> SP Per Clock Chip Select – 2 SP x SP -> DP Every Two Clocks • Multimedia Card (MMC)/Secure Digital (SD) – 2 SP x DP -> DP Every Three Clocks • Two Master and Slave Inter-Integrated Circuit (I2C – 2 DP x DP -> DP Every Four Clocks Bus™) • Fixed-Point Multiply Supports Two 32 x 32- • Programmable Real-Time Unit Subsystem Bit Multiplies, Four 16 x 16-Bit Multiplies, or (PRUSS) Eight 8 x 8-Bit Multiplies per Clock Cycle, – Two Independent Programmable Real-Time Unit and Complex Multiples (PRU) Cores – Instruction Packing Reduces Code Size • 32-Bit Load-Store RISC Architecture – All Instructions Conditional • 4KB of Instruction RAM per Core – Hardware Support for Modulo Loop • 512 Bytes of Data RAM per Core Operation • PRUSS can be Disabled Through Software – Protected Mode Operation to Save Power – Exceptions Support for Error Detection and • Register 30 of each PRU is Exported from Program Redirection the Subsystem in Addition to the Normal R31 • C674x Instruction Set Features Output of the PRU Cores – Superset of the C67x+ and C64x+ ISAs – Standard Power-Management Mechanism – 3000 MIPS and 2250 MFLOPS C674x • Clock Gating – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) • Entire Subsystem Under a Single PSC Clock – 8-Bit Overflow Protection Gating Domain – Bit-Field Extract, Set, Clear – Dedicated Interrupt Controller 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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