TMS320C6743CPTP2 datasheet(83/151 Pages) TI1

83 / 151 page

TMS320C6743

www.ti.com

SPRS565D – APRIL 2009 – REVISED JUNE 2014

Table 6-30. Ethernet Media Access Controller (EMAC) Registers (continued)

BYTE ADDRESS

0x01E2 313C

RX7FLOWTHRESH

Receive Channel 7 Flow Control Threshold Register

0x01E2 3140

RX0FREEBUFFER

Receive Channel 0 Free Buffer Count Register

0x01E2 3144

RX1FREEBUFFER

Receive Channel 1 Free Buffer Count Register

0x01E2 3148

RX2FREEBUFFER

Receive Channel 2 Free Buffer Count Register

0x01E2 314C

RX3FREEBUFFER

Receive Channel 3 Free Buffer Count Register

0x01E2 3150

RX4FREEBUFFER

Receive Channel 4 Free Buffer Count Register

0x01E2 3154

RX5FREEBUFFER

Receive Channel 5 Free Buffer Count Register

0x01E2 3158

RX6FREEBUFFER

Receive Channel 6 Free Buffer Count Register

0x01E2 315C

RX7FREEBUFFER

Receive Channel 7 Free Buffer Count Register

0x01E2 3160

MACCONTROL

MAC Control Register

0x01E2 3164

MACSTATUS

MAC Status Register

0x01E2 3168

EMCONTROL

Emulation Control Register

0x01E2 316C

FIFOCONTROL

FIFO Control Register

0x01E2 3170

MACCONFIG

MAC Configuration Register

0x01E2 3174

SOFTRESET

Soft Reset Register

0x01E2 31D0

MACSRCADDRLO

MAC Source Address Low Bytes Register

0x01E2 31D4

MACSRCADDRHI

MAC Source Address High Bytes Register

0x01E2 31D8

MACHASH1

MAC Hash Address Register 1

0x01E2 31DC

MACHASH2

MAC Hash Address Register 2

0x01E2 31E0

BOFFTEST

Back Off Test Register

0x01E2 31E4

TPACETEST

Transmit Pacing Algorithm Test Register

0x01E2 31E8

RXPAUSE

Receive Pause Timer Register

0x01E2 31EC

TXPAUSE

Transmit Pause Timer Register

0x01E2 3200 - 0x01E2 32FC

(see Table 6-31)

EMAC Statistics Registers

0x01E2 3500

MACADDRLO

MAC Address Low Bytes Register, Used in Receive Address Matching

0x01E2 3504

MACADDRHI

MAC Address High Bytes Register, Used in Receive Address Matching

0x01E2 3508

MACINDEX

MAC Index Register

0x01E2 3600

TX0HDP

Transmit Channel 0 DMA Head Descriptor Pointer Register

0x01E2 3604

TX1HDP

Transmit Channel 1 DMA Head Descriptor Pointer Register

0x01E2 3608

TX2HDP

Transmit Channel 2 DMA Head Descriptor Pointer Register

0x01E2 360C

TX3HDP

Transmit Channel 3 DMA Head Descriptor Pointer Register

0x01E2 3610

TX4HDP

Transmit Channel 4 DMA Head Descriptor Pointer Register

0x01E2 3614

TX5HDP

Transmit Channel 5 DMA Head Descriptor Pointer Register

0x01E2 3618

TX6HDP

Transmit Channel 6 DMA Head Descriptor Pointer Register

0x01E2 361C

TX7HDP

Transmit Channel 7 DMA Head Descriptor Pointer Register

0x01E2 3620

RX0HDP

Receive Channel 0 DMA Head Descriptor Pointer Register

0x01E2 3624

RX1HDP

Receive Channel 1 DMA Head Descriptor Pointer Register

0x01E2 3628

RX2HDP

Receive Channel 2 DMA Head Descriptor Pointer Register

0x01E2 362C

RX3HDP

Receive Channel 3 DMA Head Descriptor Pointer Register

0x01E2 3630

RX4HDP

Receive Channel 4 DMA Head Descriptor Pointer Register

0x01E2 3634

RX5HDP

Receive Channel 5 DMA Head Descriptor Pointer Register

0x01E2 3638

RX6HDP

Receive Channel 6 DMA Head Descriptor Pointer Register

0x01E2 363C

RX7HDP

Receive Channel 7 DMA Head Descriptor Pointer Register

0x01E2 3640

TX0CP

Transmit Channel 0 Completion Pointer Register

0x01E2 3644

TX1CP

Transmit Channel 1 Completion Pointer Register

0x01E2 3648

TX2CP

Transmit Channel 2 Completion Pointer Register

0x01E2 364C

TX3CP

Transmit Channel 3 Completion Pointer Register

Peripheral Information and Electrical Specifications

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