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TMS320C6743CPTP2 Datasheet(PDF) 49 Page - Texas Instruments |
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TMS320C6743CPTP2 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 151 page  PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV3 (/3) SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 DIV4.5 1 0 EMIFA Internal Clock Source CFGCHIP3[EMA_CLKSRC] DIV4.5 EMIFB Internal Clock Source CFGCHIP3[EMB_CLKSRC] 1 0 Pre-Div PLLM CLKMODE PLLEN AUXCLK 0 1 PLL Post-Div 1 0 Square Wave Crystal OSCIN TMS320C6743 www.ti.com SPRS565D – APRIL 2009 – REVISED JUNE 2014 The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the DSP to run from the PLL by setting PLLEN = 1. Figure 6-9. PLL Topology Copyright © 2009–2014, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 49 Submit Documentation Feedback Product Folder Links: TMS320C6743 |
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