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TMS320C6743CPTP2 Datasheet(PDF) 87 Page - Texas Instruments |
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TMS320C6743CPTP2 Datasheet(HTML) 87 Page - Texas Instruments |
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87 / 151 page  TMS320C6743 www.ti.com SPRS565D – APRIL 2009 – REVISED JUNE 2014 6.15 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more details. 6.15.1 MDIO Peripheral Register Description(s) For a list of supported MDIO registers see Table 6-35 [MDIO Registers]. Table 6-35. MDIO Register Memory Map BYTE ADDRESS REGISTER NAME REGISTER DESCRIPTION 0x01E2 4000 REV Revision Identification Register 0x01E2 4004 CONTROL MDIO Control Register 0x01E2 4008 ALIVE MDIO PHY Alive Status Register 0x01E2 400C LINK MDIO PHY Link Status Register 0x01E2 4010 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register 0x01E2 4014 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register 0x01E2 4018 – Reserved 0x01E2 4020 USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register 0x01E2 4024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register 0x01E2 4028 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 0x01E2 402C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register 0x01E2 4030 - 0x01E2 407C – Reserved 0x01E2 4080 USERACCESS0 MDIO User Access Register 0 0x01E2 4084 USERPHYSEL0 MDIO User PHY Select Register 0 0x01E2 4088 USERACCESS1 MDIO User Access Register 1 0x01E2 408C USERPHYSEL1 MDIO User PHY Select Register 1 0x01E2 4090 - 0x01E2 47FF – Reserved 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-36. Timing Requirements for MDIO Input (see Figure 6-26 and Figure 6-27) NO. MIN MAX UNIT 1 tc(MDIO_CLK) Cycle time, MDIO_CLK 400 ns 2 tw(MDIO_CLK) Pulse duration, MDIO_CLK high/low 180 ns 3 tt(MDIO_CLK) Transition time, MDIO_CLK 5 ns 4 tsu(MDIO-MDIO_CLKH) Setup time, MDIO_D data input valid before MDIO_CLK high 10 ns 5 th(MDIO_CLKH-MDIO) Hold time, MDIO_D data input valid after MDIO_CLK high 0 ns Copyright © 2009–2014, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 87 Submit Documentation Feedback Product Folder Links: TMS320C6743 |
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