TMS320C6743CPTP2 datasheet(44/151 Pages) TI1

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TMS320C6743

SPRS565D – APRIL 2009 – REVISED JUNE 2014

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6.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

6.3

Power Supplies

6.3.1

Power-On Sequence

The device should be powered-on in the following order:

1. Logic supplies:

(a) CVDD core logic supply

(b) Other static logic supplies (RVDD, PLL0_VDDA).

Groups 1a) and 1b) may be powered up together; or 1a) first, followed by 1b).

2. All digital IO supplies (DVDD).

There is no specific required voltage ramp rate for any of the supplies.

Note: Future devices may support higher performance at a higher core logic voltage (CVDD). If future

migration is desired, the current design should provide separate supplies for 1a) and 1b). If not, then 1a)

and 1b) may be provided by a single supply.

RESET must be maintained active until all power supplies have reached their nominal values.

6.3.2

Power-Off Sequence

The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered

with the other supplies unpowered.

Peripheral Information and Electrical Specifications

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TMS320C6743CPTP2 Datasheet(PDF) 44 Page - Texas Instruments