L99DZ120 datasheet(72/162 Pages) STMICROELECTRONICS

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Application information

L99DZ120

72/162

DocID029145 Rev 4

4.9.1

Features



LIN 2.2a compliant (SAEJ2602 compatible) transceiver



LIN Cell has been designed according to “Hardware requirements for transceivers

(version 1.3)”



Bitrate up to 20 kbit/s



Dedicated LIN Flash mode with bitrate up to 100 kbit/s



GND disconnection fail safe at module level



Off mode: does not disturb network



GND shift operation at system level



Micro controller Interface with CMOS-compatible I/O pins



Internal pull-up resistor



Receive-only mode



ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2



Matched output slopes and propagation delay



Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN

and Flexray Interfaces (version 1.3)

At VSREG > VPOR (i.e. VSREG power-on reset threshold), the LIN transceiver is enabled. The

LIN transmitter is disabled in case of the following errors:



Dominant TxDL time out



LIN permanent recessive



Thermal shutdown 1



VSREG overvoltage/ undervoltage

The LIN receiver is not disabled in case of any failure condition.

The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast

flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit

LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.

4.9.2

Error handling

The devices LIN transceiver provides the following 3 error handling features.

Dominant TxDL time out

If TXD_L is in dominant state (low) for t > tdom(TXDL) the transmitter will be disabled, the

status bit LIN_TXD_DOM (SR 2) will be set.

The transmitter remains disabled until the status bit is cleared.

The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).

Permanent recessive

If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < tLIN

the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.

The transmitter remains disabled until the status bit is cleared.

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