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L99DZ120 Datasheet(PDF) 96 Page - STMicroelectronics |
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L99DZ120 Datasheet(HTML) 96 Page - STMicroelectronics |
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96 / 162 page ![]() Application information L99DZ120 96/162 DocID029145 Rev 4 4.33 Analog digital converter Voltage signals VS, VSREG, VWU and TH_CL1..6 are read out sequentially. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled with the main clock fclk2 / fADC. Each channel will be converted with a conversion time tcon, therefore an update of the ADC value is available every tcon * 9. In case of WU is directly connected to Clamp 30, the input must be protected by a series resistance of typical 1kΩ to sustain reverse battery condition. Figure 48. Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 |
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