L99DZ120 datasheet(98/162 Pages) STMICROELECTRONICS

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Serial Peripheral Interface (SPI)

L99DZ120

98/162

DocID029145 Rev 4

This chapter describes the SPI protocol standardization. It defines a common structure of

the communication frames and defines specific addresses for product and status

information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the

required flexibility to adapt it to the individual functionality of a particular product. In addition,

failsafe mechanisms are implemented to protect the communication from external

influences and wrong or unwanted usage.

The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.

5.1.1

Physical layer

Figure 49. SPI pin description

5.2

Signal description



Chip Select Not (CSN)

The communication interface is de-selected, when this input signal is logically high. A

falling edge on CSN enables and starts the communication while a rising edge finishes

the communication and the sent command is executed when a valid frame was sent.

During communication start and stop the Serial Clock (SCK) has to be logically low.

The Serial Data Out (SDO) is in high impedance when CSN is high or a communication

timeout was detected.



Serial Clock (SCK)

This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is

latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on

the falling edge data from the internal shift registers are shifted out to Serial Data Out

(SDO).



Serial Data Input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising

edge of Serial Clock (SCK).



Serial Data Output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out

on the falling edge of Serial Clock (SCK).

L99DZ120 Datasheet(PDF) 98 Page - STMicroelectronics