L99DZ120 datasheet(74/162 Pages) STMICROELECTRONICS

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L99DZ120

74/162

DocID029145 Rev 4

4.10

Serial Peripheral Interface (ST SPI Standard)

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition

of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin is needed to communicate with the device. A fault condition

can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag

(fault condition) of the device.



Chip Select Not (CSN)

The input Pin is used to select the serial interface of this device. When CSN is high, the

output Pin (DO) is in high impedance state. A low signal activates the output driver and

a serial communication can be started.

The state during CSN = 0 is called a communication frame.

If CSN = low for t > tCSNfail the DO output is switched to high impedance in order not to

block the signal line for other SPI nodes.



Serial Data In (DI)

The input Pin is used to transfer data serial into the device. The data applied to the DI is

sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift

transferred to Data Input Register. The writing to the selected Data Input Register is

only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN

low). If more or less clock pulses are counted within one frame the complete frame is

ignored. This safety function is implemented to avoid an activation of the output stages

by a wrong communication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected IC's is

recommended.



Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go

from high impedance to a low or high level depending on the global error flag (fault

condition). The first rising edge of the CLK input after a high to low transition of the

CSN Pin will transfer the content of the selected status register into the data out shift



Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data

input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change

with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up

to 4 MHz.

L99DZ120 Datasheet(PDF) 74 Page - STMicroelectronics

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