MC68HC908AP16CFB datasheet(68/440 Pages) MOTOROLA

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Configuration & Mask Option Registers

Data Sheet

MC68HC908AP Family — Rev. 2.5

MOTOROLA

LVIPWRD — VDD LVI Circuit Disable Bit

LVIPWRD disables the VDD LVI circuit. (See Section 22. Low-

Voltage Inhibit (LVI).)

1 = VDD LVI circuit disabled

0 = VDD LVI circuit enabled

LVIREGD — VREG LVI Circuit Disable Bit

LVIREGD disables the VREG LVI circuit. (See Section 22. Low-

Voltage Inhibit (LVI).)

1 = VREG LVI circuit disabled

0 = VREG LVI circuit enabled

NOTE:

If LVIPWRD=1 and LVIREGD=1, set LVIRSTD=1 before entering stop

mode.

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 ICLK

cycles instead of a 4096 ICLK cycle delay.

1 = Stop mode recovery after 32 ICLK cycles

0 = Stop mode recovery after 4096 ICLK cycles

NOTE:

Exiting stop mode by pulling reset will result in the long stop recovery.

If using an external crystal oscillator, do not set the SSREC bit.

When the LVI is disabled in stop mode (LVISTOP=0), the system

stabilization time for long stop recovery (4096 ICLK cycles) gives a delay

longer than the LVI’s turn-on time. There is no period where the MCU is

not protected from a low power condition. However, when using the

short stop recovery configuration option, the 32 ICLK delay is less than

the LVI’s turn-on time and there exists a period in start-up where the LVI

is not protecting the MCU.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

Freescale Semiconductor, Inc.

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MC68HC908AP16CFB Datasheet(PDF) 68 Page - Motorola, Inc