MC68HC908AP16CFB datasheet(243/440 Pages) MOTOROLA

243 / 440 page

Serial Communications Interface Module (SCI)

I/O Registers

MC68HC908AP Family — Rev. 2.5

Data Sheet

MOTOROLA

243

Figure 13-13. Flag Clearing Sequence

PE — Receiver Parity Error Bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates an SCI error CPU interrupt request if

the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1

with PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

BYTE 1

NORMAL FLAG CLEARING SEQUENCE

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 2

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 3

BYTE 1

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC908AP16CFB Datasheet(PDF) 243 Page - Motorola, Inc

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