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PDP83TG720SWCSTQ1 Datasheet(PDF) 162 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 162 Page - Texas Instruments |
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162 / 199 page ![]() 7.6.2.104 PMA_PMD_CONTROL Register (Address = 0x1834) [reset = 0x8001] PMA_PMD_CONTROL is shown in Table 7-127. Return to the Summary Table. Table 7-127. PMA_PMD_CONTROL Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 1b1 Reserved 14 cfg_master_slave_val R/W 1b0 1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE Note - 0x1 added in [15:12] to differentiate 1b0 = Configure PHY as SLAVE 1b1 = Configure PHY as MASTER 13-4 RESERVED R 10b0000000 000 Reserved 3-0 cfg_type_selection R/W 4b0001 0000 = 100BASE-T1 0001 = 1000BASE-T1 Note - 0x1 added in [15:12] to differentiate 4b0000 = 100BASE-T1 4b0001 = 1000BASE-T1 DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 162 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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