PAC1941T-1ESLASH4MX. datasheet(24/96 Pages) MICROCHIP

24 / 96 page

PAC194X

DS20006543A-page 24

 2021 Microchip Technology Inc.

5.4

REFRESH_V Command

If the user wants to read VSENSE and VBUS results, the

most recent Power calculation and/or the accumulator

values and count without resetting the accumulators,

the REFRESH_V command may be sent. Sending the

REFRESH_V command and waiting 1 ms ensure that

the VSENSE, VBUS, Power, accumulator and accumula-

tor count values will be stable when read by the host.

The sampling of the inputs, data conversion and

power integration are not interrupted and will continue

as determined by the settings in the Control register.

The data in these readable registers will remain stable

until the next REFRESH or REFRESH_V/G command.

The internal accumulator values and accumulator

count are unaffected by the REFRESH_V command.

Note that the REFRESH_V/G command may also be

used to activate changes to the Control register, just

like the REFRESH command, except with the

REFRESH_V command, changes to the Control regis-

ter will be enacted without resetting the accumulators

or accumulator count (see Register 7-13).

5.5

Sleep State

The Sleep state is a lower power state than the Active

state. While in this state, the device will draw a supply

current of ISLEEP from the VDD pin. The device auto-

matically goes to this state between conversion cycles

when sampling rates lower than 1,024 SPS are

selected or if fewer than four channels are active. All

digital states and data are retained in Sleep state. The

device can be put in Sleep state by writing to

followed

REFRESH

REFRESH_V command, and sampling will resume

when a sampling mode is selected in this register, fol-

lowed by a REFRESH of REFRESH_V command. The

device does not go into Sleep state based on any

other condition such as static conditions on the SMBus

pins. If the SMBus time-out is enabled, it is supported

in Sleep mode or Active mode.

5.6

Power-Down State

The Power-Down state is entered only by pulling the

PWRDN pin low. In this state, all circuits on the chip

including the SMBus pins are inactive and the device

is in a state of minimum power dissipation.

In the Power-Down state, no data are retained in the

chip (neither register configuration nor measurement

data). When the PWRDN pin is pulled high,

integration, measurement and accumulation will

resume using the default register settings. The first

measurement data may be requested by a REFRESH

or REFRESH_V command 50 ms after the PWRDN

pin is pulled high.

There is a bit called POR in Register 7-10 that is set to

‘1’ on POR. This bit may be used to detect that a POR

has occurred as follows:

After the initial POR, clear this bit.

Poll the register to see if the bit is still cleared.

If the bit is set when polled, a POR has occurred

and the device needs to be reprogrammed

(unless

operating

with

the

default

programming for all registers).

5.7

Slow Sampling State and ALERT1

If the SLOW/ALERT1 pin is pulled high, the device will

sample at 8 SPS. No matter the programmed sample

rate, this new SLOW sample rate takes effect on the

next conversion cycle (if a round robin conversion

cycle is in process when the SLOW pin goes high, that

conversion cycle will complete before the SLOW

sample rate takes effect).

The SLOW pin can function as the ALERT1 pin

instead of the conversion rate control described

above. See Section 5.16, "ALERT Functionality" for

a complete discussion on the ALERT functionality,

including the ALERT2 pin. If this ALERT1 functionality

for the SLOW pin is enabled, the pin can no longer be

used to control the conversion rate. If a pull-up resistor

is attached to the SLOW/ALERT1 pin for the ALERT1

functionality, the device will power-up in Slow mode

because of being pulled up at power-up. Once the

ALERT1 functionality is assigned to the pin (see

programmed rate.

The SLOW pin functionality and the ALERT1

functionality cannot be used at the same time on this

pin.

If the SLOW pin is configured to serve as an ALERT

pin, the slower sampling rate of 8 SPS is available by

programming Register 7-2.

If the device is programmed for Single-Shot mode and

the SLOW pin is asserted, the first sampling will begin

approximately 1 ms after the SLOW pin is asserted to

allow for the analog circuitry to power up. If the device

is in the Sleep state, asserting the SLOW pin will not

cause sampling to start.

Note:

In Burst/Fast modes with one or more

channels disabled, the 1 ms REFRESH

delay will be 200 µs per channel, with an

additional 200 µs delay in Fast mode for

the calibration channel. The internal

accumulator values and accumulator

count are reset by the REFRESH

command, but the sampling of the inputs,

data conversion and power integration are

not

interrupted

and

continue

determined by the settings in the Control

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