PAC1941T-1ESLASH4MX. datasheet(27/96 Pages) MICROCHIP

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DS20006543A-page 27

PAC194X

5.12

ADC Measurements, Offset and 8X

Averaging

The PAC194X devices are primarily designed for

energy measurements where many power readings

are accumulated. This is inherently an averaging pro-

cess. Individual voltage and current measurements can

also benefit from averaging to reduce noise and offset.

Averaged values are internally calculated for VBUS and

VSENSE, with a rolling average of the most recent eight

values present in Register 7-7 and Register 7-8. The

average is updated internally after every conversion

cycle. The readable registers are updated with

REFRESH, REFRESH_V or REFRESH_G commands

like all the other readable results registers. These aver-

aged results may be used for the most accurate, lowest

noise and lowest offset measurements.

The ADC channels use a special offset canceling

technique. If users observe the unaveraged results for

near-zero values of VBUS and VSENSE, they may

observe a cyclical pattern of offset variation. The user

may think this is noise, but in fact it is due to internal

circuitry switching through different permutations of

offset cancellation circuitry. This small variation in

unaveraged offset is canceled in the 8X averaged

result and minimized in single-sample results via the

offset calibration channel. It is also canceled in the

Power Accumulator results. The overall effect is offset

that is consistently very close to zero LSB over supply

and temperature variations.

The offset canceling technique is illustrated in

Figure 5-1. It is very difficult to accurately observe, as it

is a challenge to read the data from every conversion

cycle. The effect of capturing data points at a rate that

does not correspond exactly to the internal sampling

rate of the PAC194X can make these permutations

appear less periodic and deterministic than they are

inside the chip. The data conversion uses one of the

permute positions 1-4 for each input on each conver-

sion, cycling through all four permutations in four con-

versions. When averaged, the permute enabled result

shown below is realized, evenly distributed around

zero.

FIGURE 5-1:

Illustration of the four

permute combinations that the ADC cycles

through and the resulting low average offset.

Each bin represents one code.

Results from both the VBUS and the VSENSE ADCs are

17-bit two's complement (signed) internally. There is an

additional bit of resolution that is not accessible from the

results register. Register 7-11 determines whether the

conversion results are reported in the readable registers

as unipolar or bipolar numbers. Using bipolar numbers

can give more accurate results for very small numbers

that may actually be negative for some readings, in addi-

tion to measuring bidirectional currents (charging/dis-

charging) and voltages that can dip below ground.

Averaged values are also calculated for VBUS and

VSENSE. A rolling average of the most recent eight val-

ues is present in Register 7-7 and Register 7-8. These

registers require eight conversion cycles after POR

before they represent an accurate value, they are

updated after every conversion cycle. The readable

registers are updated with REFRESH, REFRESH_V

or REFRESH_G commands like all the other readable

results registers.

100

200

300

400

500

600

700

800

900

1000

Output Code

SENSE Input Histogram vs. Permute Offset Disabled

Permute On

Permute 1

Permute 2

Permut 3

Permute 4

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