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PAC1941T-1E/4MX. Datasheet(PDF) 58 Page - Microchip Technology |
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PAC1941T-1E/4MX. Datasheet(HTML) 58 Page - Microchip Technology |
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58 / 96 page ![]() PAC194X DS20006543A-page 58 2021 Microchip Technology Inc. REGISTER 7-17: CTRL_LAT (23H) REGISTER R-0 R-0 R-0 R-0 R-0 R-1 R-1 R-1 SAMPLE_MODE[3:0] GPIO_ALERT2[1:0] SLOW_ALERT1[1:0] bit 15 bit 8 R-0 R-0 R-0 R-0 U-0 U-0 U-0 U-0 CHANNEL_N_OFF[3:0] — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown This register contains an image of Register 7-2. The bits in this register reflect the value of these settings, that was active before the most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 01h may be programmed but not activated by one of the REFRESH commands and the values in 21h are currently active. This register allows software to determine the actual active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is held in the readable registers. This reg- ister is valid when the results registers are valid, 1 ms after a REFRESH/_V/_G command. The CTRL_LAT register is not valid until the first REFRESH is sent after a POR event. bit 15-12 SAMPLE_MODE[3:0]: These bits select one of the sampling modes listed below. These modes are exclusive – that is, only one mode can be set at any given time. One of the sampling modes is Sleep, when no sampling occurs. 0b0000 = 1024 SPS adaptive accumulation (default), see Section 5.13.1, "Adaptive Accumulator" 0b0001 = 256 SPS adaptive accumulation 0b0010 = 64 SPS adaptive accumulation 0b0011 = 8 SPS adaptive accumulation 0b0100 = 1024 SPS, see Section 5.15, "Conversion Cycle Controls" 0b0101 = 256 SPS 0b0110 = 64 SPS 0b0111 = 8 SPS 0b1000 = Single-Shot mode, see Section 5.15.4, "Single-Shot Mode" 0b1001 = Single-Shot 8X 0b1010 = Fast mode, see Section 5.15.3, "Fast Mode" 0b1011 = Burst mode, see Section 5.15.2, "Burst Mode" 0b1100 = Reserved 0b1101 = Reserved 0b1110 = Reserved 0b1111 = Sleep, see Section 5.5, "Sleep State" bit 11-10 GPIO_ALERT2[1:0]: Select the signals for the GPIO/ALERT2 pin. If the pin is configured as a GPIO pin, the R/W data for the pin are stored in Register 7-10. 00 = ALERT functions as an ALERT pin 01 = GPIO digital input. Read the digital value input to this pin from Register 7-10. Default for this pin. 10 = GPIO digital output. Write the digital value to be output from this pin to Register 7-10. 11 = The pin functions as the SLOW pin, taking the pin high overrides the programmed sample rate and yields a sampling rate of 8 SPS. bit 9-8 SLOW_ALERT1[1:0]: Select the signals for SLOW/ALERT1 pin. If the pin is configured as a GPIO pin, the R/W data for the pin are stored in Register 7-10. 00 = ALERT functions as an ALERT1 pin 01 = GPIO digital input. Read the digital value input to this pin from Register 7-10. 10 = GPIO digital output. Write the digital value to be output from this pin to Register 7-10. 11 = SLOW functions as the SLOW pin, taking the pin high overrides the programmed sample rate and yields a sampling rate of 8 SPS (default for this pin). |
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