PAC1941T-1ESLASH4MX. datasheet(29/96 Pages) MICROCHIP

29 / 96 page

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DS20006543A-page 29

PAC194X

As shown in Equation 5-8 and Equation 5-9, it is

necessary to know the sampling frequency and sam-

pling period for each interval that we want to accumu-

late energy over. If the SLOW pin is used and the

period changes, the accumulator value and count

must be fetched and calculated each time the sam-

pling rate changes. With the adaptive accumulator, the

data only need to be fetched before the accumulator

and/or accumulator count overflow and an accurate

energy calculation can be made, independent of how

many times the SLOW pin was asserted and

deasserted during the period. The sample rate for

these calculations is the programmed sample rate.

Because the Adaptive Accumulator mode is the

default mode, the feature of an internal REFRESH

being generated on assertion/deassertion of the

SLOW pin is defaulted to inactive. The user must man-

ually program a REFRESH on SLOW pin transition, if

desired, using Register 7-14.

By programming one of the adaptive accumulator

sampling rates in Register 7-2 other than 1024 SPS,

the accumulator and accumulator count will shift the

data and count to mimic accumulation at 1024 SPS.

5.13.2

ADDITIONAL ACCUMULATOR

INFORMATION

The math for the power calculation and accumulation

inside the chip is always done in two's complement

math, no matter what the user sets the output registers

to show. VBUS and VSENSE are 17-bit two's

complement (signed) numbers internally. VPOWER is

the product of VSENSE multiplied by the 14 MSBs of

VBUS and this is a 30-bit two's complement result

(signed) internally. In some cases, this results in a

power result that is not identical to the product of the

VBUS results register multiplied by the VSENSE register.

However, the power result from the VPOWER results

cases, as explained below.

If VSENSE and VBUS are both programmed to be

unsigned (unipolar) in register Register 7-11, 16 bits

without sign are exported to the VBUS and VSENSE

results registers.

If VBUS is programmed to be signed (bipolar) in

16-bit two's complement (signed) for the readable

results register.

If VSENSE is programmed to be signed (bidirectional) in

but

the

power

calculation

uses

17-bit

two's

complement. Therefore, a mismatch is possible

between an externally calculated power value (VBUS

times VSENSE) and the actual power value calculated

internally to the chip.

The internally calculated (and accumulated) value is

more accurate than the externally calculated value in

every case.

This is also true for FSR/2 modes, in that the FSR/2

mode uses bit shifting to change the FSR so no accu-

racy is lost in the power calculation (similar to Unipolar

mode).

The continuous power integration periods (also called

energy accumulation periods) can range from ~1 ms to

many hours, depending on the number of samples per

second selected via SMBus. The number of samples is

limited by the size of the Accumulator Count register to

4,294,967,296 (232). This count corresponds to about

1165 hours at 1024 SPS or about 17 years at 8 SPS.

This accumulator count can overflow and it will not

reset when it overflows.

When the accumulation registers reach their maximum

value, this is called accumulator overflow. The

accumulator outputs remain at their maximum value;

they do not rollover. The user can calculate the

worst-case time to saturation and read them at or

before that time or use the accumulator fullness limits

to detect when the accumulators and/or accumulator

count are 15/16, 7/8, 3/4 or completely full and read

and/or reset them at that time (see Register 7-23).

Worst-case accumulator overflow time can be

calculated assuming that every measurement that is

accumulated is a full-scale number. Since the power

numbers are 30 bits and the accumulator is 56 bits, 226

samples can be accumulated before overflow, if they

are all full-scale values. For most applications, they will

not all be full-scale numbers; this is especially true if

VBUS is nominally less than the maximum VBUS for the

device. If the maximum VBUS for the system is always

lower than FSR for VBUS, the maximum number of

full-scale samples that can be accumulated is scaled

by FSR/VBUS maximum for the system. If both VBUS

and VSENSE values are always near full scale, this can

limit the accumulation period before overflow to 1092

minutes at 1024 SPS or 2330 hours at 8 SPS. If

sample values are well below full scale, the user can

calculate how many samples can be accumulated

before the accumulator will overflow. As described

above, the accumulator count will likely not limit the

number of samples that can be accumulated and

counted.

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