PAC1941T-1ESLASH4MX. datasheet(59/96 Pages) MICROCHIP

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DS20006543A-page 59

PAC194X

bit 7-4

CHANNEL_N_OFF[3:0]:

Allow one or more channels to be inactive during the conversion cycle. These settings apply for normal

continuous round robin conversion cycles or Single-Shot mode, if Single-Shot mode is selected. If a

channel is set to inactive, the auto-incrementing address pointer will skip addresses associated with

that channel unless the pointer skipping bit 1 in this register is set.

In PAC194X devices, deactivating channels allows faster sampling. Burst or Fast modes are selected

using bits [15:12] in this register.

PAC1944-1 default = 0b0000 (register default 0700h) (shown above)

PAC1943-1 default = 0b0001 (register value 0710h)

PAC1942-1 default = 0b0011 (register value 0730h)

PAC1942-2 default = 0b0011 (register value 0730h)

PAC1941-1 default = 0b0111 (register value 0770h)

PAC1941-2 default = 0b0111 (register value 0770h)

bit 3-0

Unimplemented, read as ‘0’.

NEG_PWR_FSR _LAT (24H) REGISTER

R/W-0

CFG_VS1[1:0]

CFG_VS2[1:0]

CFG_VS3[1:0]

CFG_VS4[1:0]

bit 15

bit 8

R/W-0

CFG_VB1[1:0]

CFG_VB2[1:0]

CFG_VB3[1:0]

CFG_VB4[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

This register holds an image of Register 7-11. The bits in this register reflect the settings that were active before the

most recent REFRESH command (including REFRESH_V and/or REFRESH_G). The values in register 1Dh may be

programmed but not activated by one of the REFRESH commands. This register shows the settings that were active

prior to the most recent REFRESH command and therefore correspond to the dataset that is held in the readable reg-

isters. This register is valid when the results registers are valid, 1 ms after a REFRESH/_V/_G command.

bit 15-14

CFG_VS1[1:0]: Configure Channel 1 FSR for VSENSE measurements

00 = Channel 1 VSENSE has unipolar +100 mV to 0V FSR (default)

01 = Channel 1 VSENSE has bipolar +100 mV to -100 mV FSR

10 = Channel 1 VSENSE has bipolar +50 mV to -50 mV FSR

11 = Reserved

bit 13-12

CFG_VS2[1:0]: Configure Channel 2 FSR for VSENSE measurements

00 = Channel 2 VSENSE has unipolar +100 mV to 0V FSR (default)

01 = Channel 2 VSENSE has bipolar +100 mV to -100 mV FSR

10 = Channel 2 VSENSE has bipolar +50 mV to -50 mV FSR

11 = Reserved

bit 11-10

CFG_VS3[1:0]: Configure Channel 3 FSR for VSENSE measurements

00 = Channel 3 VSENSE has unipolar +100 mV to 0V FSR (default)

01 = Channel 3 VSENSE has bipolar +100 mV to -100 mV FSR

10 = Channel 3 VSENSE has bipolar +50 mV to -50 mV FSR

11 = Reserved

CTRL_LAT (23H) REGISTER (CONTINUED)

PAC1941T-1E/4MX. Datasheet(PDF) 59 Page - Microchip Technology

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