PAC1941T-1ESLASH4MX. datasheet(51/96 Pages) MICROCHIP

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DS20006543A-page 51

PAC194X

SMBUS SETTINGS (1CH) REGISTER

R/W-0

R/W-1

R/W-0

GPIO_

DATA2

GPIO_

DATA1

ANY_ALERT

POR

TIMEOUT

BYTE

COUNT

NO SKIP

I2C_

HISPEED

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Bits in this register may be written or read at any time and are active immediately. Refresh is not required to activate

them or update them.

bit 7

GPIO_DATA2: R/W data for the pin GPIO/ALERT2 if the pin is configured as a GPIO pin. See

0 = Pull the GPIO pin low when configured to be an output (default)

1 = GPIO pin pulled to external VIO via an external resistor when configured to be an output

bit 6

GPIO_DATA1: R/W data for the pin SLOW/ALERT1 if the pin is configured as a GPIO pin. See

0 = Pull the GPIO pin low when configured to be an output (default)

1 = GPIO pin pulled to external VIO via an external resistor when configured to be an output

bit 5

ANY_ALERT: This bit is set by any of the active ALERT functions being triggered, except ALERT_CC.

This bit is cleared when the ALERT function that set the bit is cleared. See Section 5.16.2, "ALERT

Pin Assignments".

0 = No ALERT condition has occurred (default)

1 = An ALERT condition has occurred, read Register 7-20 for cause

bit 4

POR: The POR bit is for the purpose of enabling the system designer to learn if the chip is reset after

it is programed. The user can clear this bit after POR and then monitor it to detect if the device was

powered cycled or somehow reset since the POR. If the reset is detected in this manner, any

non-default programming can be reprogrammed. This bit is only reset by the internal POR, which can

occur from power cycling or the PWRDN pin going low.

0 = This bit has been cleared over I2C since the last POR occurred

1 = Default. This bit has the POR default value of ‘1’ and has not been cleared since the last reset

occurred

bit 3

TIMEOUT enable bit. The SMBus time-out is disabled by default and is enabled by setting this bit.

0 = No SMBus time-out feature (default)

1 = SMBus time-out feature is available

bit 2

BYTE COUNT: This bit causes Byte Count data to be included in the response to the SMBus Block

Read command for each register read. This functionality is disabled by default and Block Read

corresponds to the I2C protocol.

0 = No Byte Count in response to a Block Read command (default)

1 = Data in response to a Block Read command include the Byte Count data

bit 1

NO SKIP: This bit controls the auto-incrementing of the address pointer for channels that are inactive.

0 = The auto-incrementing pointer will skip over addresses used by/for channels that are inactive

(default)

1 = The auto-incrementing pointer will not skip over addresses used by/for channels that are inactive.

When these channels are disabled, if a read is performed, it will read FF.

bit 0

I2C_HISPEED: Setting this bit enables the 3.4 MHz I2C operation by changing the pulse-width

parameters of the Pulse Gobbler. Default = 0.

PAC1941T-1E/4MX. Datasheet(PDF) 51 Page - Microchip Technology

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