PAC1941T-1ESLASH4MX. datasheet(34/96 Pages) MICROCHIP

34 / 96 page

PAC194X

DS20006543A-page 34

 2021 Microchip Technology Inc.

6.1.5

SMBUS DATA BYTES

All SMBus data bytes are sent MSb first and

composed of 8 bits of information.

6.2

SMBus Time-out

The PAC194X devices can support the SMBus

time-out functionality. This functionality is disabled by

default and can be enabled by writing to the TIMEOUT

bit (see Register 7-10).

If time-out is enabled and the clock is held at logic ‘0’

for 25 ms-35 ms, the device will time-out and reset the

SMBus interface. Communication is restored with a

Start condition.

6.3

SMBus and I2C Compatibility

The PAC194X devices are compatible with the SMBus

3.1 1 MHz class and the I2C Fast mode Plus. The

major differences between SMBus and I2C devices

are highlighted below (for more information, refer to

the SMBus 3.1 and I2C specifications):

The minimum frequency for SMBus communi-

cations is 10 kHz, if the time-out function is

enabled. If the time-out function is disabled

(default condition), there is no minimum

frequency for SMBus communications.

I2C does not have a time-out, this is the default

condition. The SMBus client protocol will reset if

the clock is held at a logic ‘0’ for tTIMEOUT, if

SMBus time-out is enabled in Register 7-10.

I2C devices do not support the Alert Response

Address functionality (which is optional for

SMBus). The PAC194X does not support the

Alert Response Address functionality. Instead,

the ALERT pin, when configured for ALERT, is

an open-drain output pin that may be monitored

by the host or embedded controller.

I2C devices support Block Read and Block Write

differently. The I2C protocol allows for an

unlimited number of bytes to be sent in either

direction. The SMBus protocol for Block Read

and Block Write requires that an additional data

byte indicating the number of bytes to read/write

is transmitted. The PAC194X devices support

the I2C protocol for Block Read by default (no

byte count information is sent). If the Byte Count

bit is set (see Register 7-10), the Byte Count will

be sent as the first data byte in response to the

Block Read command, per SMBus protocol.

SMBus uses fixed logic thresholds for logical

high and low signals. I2C uses levels that are

proportional to VDD. PAC194X uses fixed logic

levels of 0.8V and 1.35V, as specified by

SMBus.

TABLE 6-1:

ADDRESS SELECT

RESISTOR

Resistor (1%)

SMBus Address

0 (GND)

0010 000 (R/W)

499

0010 001 (R/W)

806

0010 010 (R/W)

1,270

0010 011 (R/W)

2,050

0010 100 (R/W)

3,240

0010 101 (R/W)

5,230

0010 110 (R/W)

8,450

0010 111 (R/W)

13,300

0011 000 (R/W)

21,500

0011 001 (R/W)

34,000

0011 010 (R/W)

54,900

0011 011 (R/W)

88,700

0011 100 (R/W)

140,000

0011 101 (R/W)

226,000

0011 110 (R/W)

Tie to VDD

0011 111 (R/W)

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