LSM6DSV320X datasheet(105/212 Pages) STMICROELECTRONICS

105 / 212 page

9.69

MD2_CFG (5Fh)

Functions routing to INT2 pin register (R/W). Each bit in this register enables a signal to be carried over the INT2

pin. The output of the pin is the OR combination of the signals selected here and in the INT2_CTRL (0Eh)

Table 185. MD2_CFG register

INT2_SLEEP

_CHANGE

INT2_

SINGLE_TAP

INT2_WU

INT2_FF

INT2_

DOUBLE_TAP

INT2_6D

INT2_

EMB_FUNC

INT2_

TIMESTAMP

Table 186. MD2_CFG register description

INT2_SLEEP_CHANGE(1)

Routing activity/inactivity recognition event to INT2. Default: 0

(0: routing activity/inactivity event to INT2 disabled;

1: routing activity/inactivity event to INT2 enabled)

INT2_SINGLE_TAP

Single-tap recognition routing to INT2. Default: 0

(0: routing single-tap event to INT2 disabled;

1: routing single-tap event to INT2 enabled)

INT2_WU

Routing wake-up event to INT2. Default value: 0

(0: routing wake-up event to INT2 disabled;

1: routing wake-up event to INT2 enabled)

INT2_FF

Routing free-fall event to INT2. Default value: 0

(0: routing free-fall event to INT2 disabled;

1: routing free-fall event to INT2 enabled)

INT2_DOUBLE_TAP

Routing tap event to INT2. Default value: 0

(0: routing double-tap event to INT2 disabled;

1: routing double-tap event to INT2 enabled)

INT2_6D

Routing 6D event to INT2. Default value: 0

(0: routing 6D event to INT2 disabled;

1: routing 6D event to INT2 enabled)

INT2_EMB_FUNC

Routing embedded functions event to INT2. Default value: 0

(0: routing embedded functions event to INT2 disabled;

1: routing embedded functions event to INT2 enabled)

INT2_TIMESTAMP

Enables routing the alert for timestamp overflow within 5.6 ms to the INT2 pin.

1. Activity/inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the

INACTIVITY_DUR (54h) register.

9.70

HAODR_CFG (62h)

HAODR data rate configuration register (R/W)

Table 187. HAODR_CFG register

0(1)

HAODR_

SEL_1

HAODR_

SEL _0

1. This bit must be set to 0 for the correct operation of the device.

Table 188. HAODR_CFG register description

HAODR_SEL_[1:0]

Selects the ODR set supported when high-accuracy ODR (HAODR) mode is enabled (see Table 22).

Default: 00

LSM6DSV320X

DS14623 - Rev 1

page 105/212

LSM6DSV320X Datasheet(PDF) 105 Page - STMicroelectronics

LSM6DSV320X Datasheet(HTML) 105 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL