H8SLASH300H datasheet(48/552 Pages) RENESAS

48 / 552 page

Section 2 CPU

Rev. 3.00 May 15, 2007 Page 16 of 516

REJ09B0152-0300

2.4

Instruction Set

2.4.1

Table of Instructions Classified by Function

The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each

functional category. The notation used in tables 2.2 to 2.9 is defined below.

Table 2.1

Operation Notation

Symbol

Description

General register (destination)*

General register (source)*

General register*

ERn

General register (32-bit register or address register)

(EAd)

Destination operand

(EAs)

Source operand

CCR

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

–

Subtraction

Multiplication

Division

∧

Logical AND

∨

Logical OR

⊕

Logical XOR

→

Move

NOT (logical complement)

:3/:8/:16/:24

3-, 8-, 16-, or 24-bit length

Note:

General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).

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