H8SLASH300H datasheet(92/552 Pages) RENESAS

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Section 3 Exception Handling

Rev. 3.00 May 15, 2007 Page 60 of 516

REJ09B0152-0300

3.8.3

Method for Clearing Interrupt Request Flags

Use the recommended method given below when clearing the flags in interrupt request registers

(IRR1 and IRR2).

• Recommended method

Use a single instruction to clear flags. The bit manipulation instruction and byte-size data

transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in

IRR1) are given below.

Example 1:

BCLR

#1,

@IRR1:8

Example 2:

MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)

• Example of a malfunction

When flags are cleared with multiple instructions, other flags might be cleared during

execution of the instructions, even though they are currently set, and this will cause a

malfunction.

Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1

(bit 1 in IRR1).

MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time

AND.B #B'11111101,R1L ..... Here, IRRI0 = 1

MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0

In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B

instruction is executing.

The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,

IRRI0 is also cleared.

3.8.4

Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction

such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the

interrupt concerned will still be enabled on completion of the instruction, and so interrupt

exception handling for that interrupt will be executed on completion of the instruction. When an

interrupt source flag is cleared to 0, the interrupt concerned will be ignored.

H8/300H Datasheet(PDF) 92 Page - Renesas Technology Corp