H8SLASH300H datasheet(95/552 Pages) RENESAS

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Section 4 Clock Pulse Generators

CPG0200A_000020020200

Rev. 3.00 May 15, 2007 Page 63 of 516

REJ09B0152-0300

Section 4 Clock Pulse Generators

The clock pulse generator is provided on-chip, including both a system clock pulse generator and

a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,

system clock divider, and on-chip oscillator. The subclock pulse generator consists of a subclock

oscillator, on-chip oscillator clock divider, and subclock divider. Figure 4.1 shows a block

diagram of the clock pulse generators.

System

clock

oscillator

On-chip

oscillator

OSCCR

Subclock

oscillator

Subclock

divider

System

clock

divider

On-chip

oscillator

clock divider

Prescaler S

(13 bits)

OSC

E7_2

OSC2

System clock pulse

generator

Subclock pulse generator

[Legend]

OSCCR: Oscillator control register

φOSC

(fOSC)

φOSC

(fOSC)

φW

(fW)

φW

(fW)

φW/2

φW/4

φSUB

φ/2

φ/8192

φW

φW/4

φW/2

φW/8

φOSC/8

φOSC

φOSC/16

φOSC/32

φOSC/64

Prescaler W

(8 bits)

W/8

W/1024

Rosc/32

Rosc

(fROSC)

Rosc

Figure 4.1 Block Diagram of Clock Pulse Generators

The reference clock signals that drive the CPU and on-chip peripheral modules are

φ and φ

SUB. The

system clock is divided by prescaler S to become a clock signal from

φ/8192 to φ/2. φ

W/4, which is

1/4th of the watch clock

W, is divided by prescaler W to become a clock signal from φW/1024 to

W/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.

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