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H8/300H Datasheet(PDF) 64 Page - Renesas Technology Corp

Part # H8/300H
Description  Renesas 16-Bit Single-Chip Microcomputer
PDF  552 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/300H Datasheet(HTML) 64 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 3.00 May 15, 2007 Page 32 of 516
REJ09B0152-0300
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (
φ) or a subclock (φ
SUB). The period from a rising
edge of
φ or φ
SUB to the next rising edge is called one state. A bus cycle consists of two states.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T1 state
Bus cycle
T2 state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
SUB
φ or φ
Figure 2.9 On-Chip Memory Access Cycle



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